YorChip announces Universal PHYTM PPA and introduces Open PHY to jumpstart broader market

“Universal PHYTM is designed for both logic and memory over UCIe. The PHY cell supports TX, RX and switches modes rapidly a feature critical for HBM & HBF.”

SAN RAMON, CA, UNITED STATES, October 14, 2025 /EINPresswire.com/ -- YorChip, Inc. today announced the design completion of its Universal PHYTM, enabling customers to develop Open Chiplets and ASIC solutions for low power, cost-sensitive markets. The fully digital PHY, based on the UCIe-3D architecture, delivers power consumption below 0.1 pj/bit and area footprint of 0.07 mm2. The initial version targets digital logic interconnects – but the Universal PHY is designed to support future memory interfaces such as HBM over UCIe, HBF over UCIe and advanced NVM over UCIe applications.

The company also introduced a free Open PHY specification, which is interoperable with the Universal PHYTM for universities, inventors, and startups to accelerate Chiplet innovation. The Open PHY is suitable for mature nodes as well as specialty Optical, Memory and Mems nodes to join the multi-die revolution in a single package.

YorChip’s CEO and co-founder, Kash Johal, said “YorChip supports the Open Chiplet Economy initiative from OCP with our OpenPHY. Broad use of Chiplets is not happening due to PHY licensing costs (millions of dollars), lack of availability on mature nodes and OpenPHY will help jumpstart Chiplet adoption by eliminating cost and design barriers.”

YorChip’s CTO and co-founder, Frank Dunlap, said, “Universal PHYTM offers best in class Power and Area and is designed to support in-package connectivity for both logic and memory over UCIe. Our core PHY cell may be configured as either TX, RX and switches modes rapidly, a feature critical for future HBM, HBF and NVM applications which require asymmetric bandwidth.”

“Open chiplet architectures are redefining how innovation scales by enabling seamless die-to-die interoperability and lowering barriers to entry. QuickLogic is committed to accelerating this future by developing flexible, low-power interfaces and working hand-in-hand with partners like YorChip to make the Open Chiplet Economy a reality,” said Brian Faith, CEO of QuickLogic.
YorChip will be at Global Summit October 13-16 in San Jose, California, exhibiting in the innovation village area.

About YorChip
Yorchip is developer of UCIe PHY IP for Chiplets featuring best in class PPA. Our UCIe PHY is designed to be portable across any foundry and node – it’s 100% digital. YorChip is working with a number of Partners to offer Chiplets to end customers across a broad range of markets by leveraging our Universal PHYTM and advanced packaging technology. YorChip is headquartered in San Ramon, California with design partners worldwide.

kashmira johal
YorChip Inc.
+1 408-390-8649
email us here

Legal Disclaimer:

EIN Presswire provides this news content "as is" without warranty of any kind. We do not accept any responsibility or liability for the accuracy, content, images, videos, licenses, completeness, legality, or reliability of the information contained in this article. If you have any complaints or copyright issues related to this article, kindly contact the author above.